The present invention relates to a MOS field effect transistor with an improved lightly doped diffusion layer structure and more particularly to a MOS field effect transistor having refractory metal silicide layers on a gate, and source and drain layers as well as a method of forming the same.
The requirements for scaling down the semiconductor devices and increase in density of integration of the semiconductor devices have been on the increase. At present, 0.25 micrometers scale rule has been applied to design the advanced semiconductor devices such as logic devices.
The scaling down of the semiconductor device is most effective to realize a further increase in density of integration of the semiconductor device and an improvement in high speed performances thereof, for which reason how to scale down the semiconductor device as much as possible an essential issue to be realized. In order to realize a substantive scale down of the semiconductor devices, it is required to form shallow diffusion layers as source and drain regions in the MOS field effect transistor. However, the shallow diffusion layers results in a high resistance of the source and drain regions. The increase in resistance of the source and drain regions results in a remarkable drop of a current driving ability of the MOS field effect transistor. This makes it difficult to improve high speed performances of the MOS field effect transistor. Accordingly, there exist serious problems with an increased resistance of the source and drain regions due to the formation of the shallow source and drain regions for scaling down of the MOS field effect transistors.
In order to solve the above problems, it has been proposed to form metal silicide layers on the gate, and the source and drain regions, wherein the metal silicide layers have a lower resistivity. Namely, a proposal was made for forming the MOS field effect transistor with the silicide structure or a self-aligned silicide structure often referred to as a salicide structure.
The silicide structure, however, raises another problem with likelihood of formation of short circuit between source/drain diffusion layers and the gate of the MOS field effect transistor.
In Japanese laid-open patent publication No. 8-204188, it is disclosed to attempt settlement of the above other problem with the short circuit. A conventional fabrication method of the MOS field effect transistor will be described with reference to FIGS. 1A through 1C.
With reference to FIG. 1A, a p-type silicon substrate 21 is used. Field oxide films 22 are selectively formed on a surface of the p-type silicon substrate 21 to define an active region on which a MOS field effect transistor will be formed. A gate oxide film 23 is formed on an active region of the p-type silicon substrate 21. A polysilicon gate electrode 24 is formed on the gate oxide film 23. The polysilicon gate electrode 24 and the field oxide films 22 are used as masks for ion-implantation of an n-type impurity into the surface region of the p-type silicon substrate 21 and subsequent heat treatment to the p-type silicon substrate 21 for causing a thermal diffusion of ion-implanted n-type impurity, whereby shallow lightly-doped diffusion regions 25 are formed in upper regions of the p-type silicon substrate 21 except under the gate electrode 24 and under the field oxide films 22. A chemical vapor deposition is carried out to entirely deposit a silicon oxide film 26 having a thickness of about 50 nanometers so that the silicon oxide film 26 covers the field oxide films 22 and the lightly doped diffusion regions 25 as well as side walls and a top surface of the polysilicon gate electrode 24. Further, a silicon nitride film 27 having a thickness of about 70 nanometers is then formed on the silicon oxide film 26 thereby forming laminations of the silicon oxide film 26 and the silicon nitride film 27.
With reference to FIG. 1B, a reactive ion etching is carried out to the laminations of the silicon oxide film 26 and the silicon nitride film 27 so that the silicon oxide film 26 and the silicon nitride film 27 are subjected to the etch-back whereby the laminations of the silicon oxide film 26 and the silicon nitride film 27 remain only on the side walls of the polysilicon gate electrode 24. As a result, the laminations of the silicon oxide film 26 and the silicon nitride film 27 are made into laminations of a side wall silicon oxide film 28 and a side wall silicon nitride film 29 which are provided on the side walls of the polysilicon gate electrode 24. An ion-implantation of an n-type impurity into the silicon substrate 1 is carried out by use of the side wall silicon oxide films 28 and the side wall silicon nitride films 29 as masks for subsequent heat treatment thereby to form source/drain diffusion layers 30.
With reference to FIG. 1C, a titanium film having a thickness of about 50 nanometers is entirely deposited which extends on the field oxide films and over the source/drain diffusion layers 30 as well as on the side wall silicon nitride films 29 and over the side wall silicon oxide films 28 and a top surface of the polysilicon gate electrode 24. A heat treatment to the silicon substrate 1 in an inert gas such as a nitrogen gas to cause a silicidation reaction between silicon and titanium atoms whereby titanium silicide layers 31 are selectively formed on the top surface of the polysilicon gate electrode 24 and on the source/drain diffusion layers 30, whilst no silicidation reaction is caused over the field oxide films 22 and on the side wall silicon nitride films 29 and the side wall silicon oxide films 28. The unreacted titanium film is removed.
The source/drain diffusion layers 30 have the silicide structure and the lightly-doped diffusion structure. The polysilicon gate electrode 24 also has the silicide structure.
The above conventional MOS field effect transistor, however, has the following four problems.
The first problem is concerned with an overlap of the lightly-doped diffusion layer 25 and the polysilicon gate electrode 24 as illustrated in FIG. 2. Namely, the lightly-doped diffusion layers 25 are formed by ion-implantation of the impurity by use of the polysilicon gate electrode 24 as the mask whereby the inside edges of the lightly doped diffusion layers 25 are positioned under the outside edge of the polysilicon gate electrode 24. Thereafter, to form the source and drain diffusion layers 30, the heat treatment is caused. This heat treatment, however, causes further diffusions inwardly of the lightly doped diffusion layers 25, whereby the inside edges of the lightly doped diffusion layers are moved into inside of the outside edges of the polysilicon gate electrode 24. As a result, the inside end portions of the lightly doped diffusion layers 25 are positioned under the polysilicon gate electrode 24, for which reason there are formed overlaps between the lightly doped diffusion layers 25 and the polysilicon gate electrode 24. Particularly if the 0.25 micrometers scale rule is applied to design of the MOS field effect transistor, the overlap between the lightly doped diffusion layers 25 and the polysilicon gate electrode 24 is not ignorable. This further makes it difficult to control a channel length of the conventional MOS field effect transistor.
The second problem is concerned with a difficulty in control of etch-back to form the side wall silicon oxide films 28 and the side wall silicon nitride films 29. Namely, the above conventional MOS field effect transistor has a multi-layered or double-layered side wall insulator structure comprising laminations of the silicon oxide film 28 and the silicon nitride film 29. The multi-layered or double-layered side wall insulator structure makes it difficult to do a precise control of the etch-back due to different materials of the double layers. This problem is more remarkable if the MOS field effect transistor is scaled down.
The third problem is concerned with an increase in parasitic capacitance between the polysilicon gate electrode 24 and the source/drain diffusion layers 30. Namely, the side wall insulation layers 28 and 29 as dielectric films are formed on the side walls of the polysilicon gate electrode 24. Particularly, the silicon nitride films 29 have a high dielectric constant. For those reasons, the formations of the side wall insulation layers 28 and 29 on the side walls of the polysilicon gate electrode 24 result in increase in fringe capacitance or parasitic capacitance.
The fourth problem is concerned with an insulating resistance between the adjacent two polysilicon gate electrodes 24. The polysilicon gate electrodes 24 are defined by a dry etching to a polysilicon layer extending over the gate insulation film and also over the field oxide films 22. There are steps with a difference in level at boundaries between the gate insulation film 23 and the field oxide films 22. In the dry etching process, the polysilicon layer is likely to reside on the steps between the gate insulation film 23 and the field oxide films 22. The residual polysilicon films on the steps between the gate insulation film 23 and the field oxide films 22 may cause a slight leakage of current between the adjacent two polysilicon gate electrodes. The likelihood of causing the slight leakage of current between the adjacent two polysilicon gate electrodes is increased if the MOS field effect transistors are scaled down and the density of integration of the MOS field effect transistors is increased.
In the above circumstances, it had been required to develop a novel MOS field effect transistor with a side wall insulation structure free from the above first to fourth problems.